3XX Datasheet, PDF (59/82 Pages) Intel Corporation – Celeron D Processor

Pin Listing and Signal Descriptions
Table 4-3. Signal Description (Sheet 6 of 8)
Name
OPTIMIZED/
COMPAT#
PROCHOT#
PWRGOOD
REQ[4:0]#
RESET#
RS[2:0]#
RSP#
SKTOCC#
Type
Description
Input
This is an input to the processor to determine if the processor is in an optimized
platform or a compatible platform. This input has a weak internal pull-up.
A compatible platform is one that is designed for a previous generation
processor but has some level of compatibility with the Celeron D processor. An
optimized platform is one designed specifically for the Celeron D processor;
however, it may have some level of compatibility with previous generation
processors.
Input/
Output
As an output, PROCHOT# (Processor Hot) goes active when the processor
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system activates the TCC, if enabled. The TCC remains
active until the system de-asserts PROCHOT#.
Input
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable and
within their specifications. ‘Clean’ implies that the signal will remain low (capable
of sinking leakage current), without glitches, from the time that the power
supplies are turned on until they come within specification. The signal must then
transition monotonically to a high state. PWRGOOD can be driven inactive at
any time, but clocks and power must again be stable before a subsequent rising
edge of PWRGOOD. It must also meet the minimum pulse width specification
and be followed by a 1 ms to 10 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
Input/
Output
REQ[4:0]# (Request) must connect the appropriate pins of all processor FSB
agents. They are asserted by the current bus owner to define the currently active
transaction type. These signals are source synchronous to ADSTB0#. Refer to
the AP[1:0]# signal description for a details on parity checking of these signals.
Input
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least 1 ms after V_CC and BCLK
have reached their proper specifications. On observing active RESET#, all FSB
agents will de-assert their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are described
in the Section 6.1.
This signal does not have on-die termination and must be terminated on the
system board.
Input
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of all processor FSB agents.
Input
RSP# (Response Parity) is driven by the response agent (the agent responsible
for completion of the current transaction) during assertion of RS[2:0]#, the
signals for which RSP# provides parity protection. It must connect to the
appropriate pins of all processor FSB agents.
A correct parity signal is high if an even number of covered signals are low and
low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is
also high, since this indicates it is not being driven by any agent guaranteeing
correct parity.
Output
SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System
board designers may use this pin to determine if the processor is present.
Datasheet
59