3XX Datasheet, PDF (57/82 Pages) Intel Corporation – Celeron D Processor

Pin Listing and Signal Descriptions
Table 4-3. Signal Description (Sheet 4 of 8)
Name
DRDY#
Type
Description
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be de-asserted to insert idle clocks. This signal must connect the
appropriate pins of all processor FSB agents.
Data strobe used to latch in D[63:0]#.
DSTBN[3:0]#
Input/
Output
Signals
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP[3:0]#
Data strobe used to latch in D[63:0]#.
Input/
Output
Signals
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
FERR#/PBE#
GTLREF
HIT#
HITM#
IERR#
Output
FERR#/PBE# (Floating Point Error/Pending Break Event) is a multiplexed signal
and its meaning is qualified by STPCLK#. When STPCLK# is not asserted,
FERR#/PBE# indicates a floating-point error and will be asserted when the
processor detects an unmasked floating-point error. When STPCLK# is not
asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using MS-DOS*-type
floating-point error reporting.
When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the
processor has a pending break event waiting for service. The assertion of
FERR#/PBE# indicates that the processor should be returned to the Normal
state. For additional information on the pending break event functionality,
including the identification of support of the feature and enable/disable
information, refer to volume 3 of the Intel Architecture Software Developer's
Manual and the Intel Processor Identification and the CPUID Instruction
application note.
Input
GTLREF determines the signal reference level for GTL+ input pins. GTLREF is
used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.
Refer to the applicable chipset platform design guide for more information.
Input/
Output
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any FSB agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
Output
IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction
on the processor FSB. This transaction may optionally be converted to an
external error signal (e.g., NMI) by system core logic. The processor will keep
IERR# asserted until the assertion of RESET#.
This signal does not have on-die termination. Refer to Section 2.5 for termination
requirements.
Datasheet
57