3XX Datasheet, PDF (11/82 Pages) Intel Corporation – Celeron D Processor

1 Introduction
Introduction
The Intel^® Celeron^® D processor on 90 nm process and in the 478-pin package uses Flip-Chip Pin
Grid Array 4 (FC-mPGA4) package technology, and plugs into a 478-pin surface mount, Zero
Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Celeron D processor on
90 nm process and in the 478-pin package is based on the same Intel 32-bit microarchitecture and
maintains the tradition of compatibility with IA-32 software.
Note: In this document the Celeron D processor on 90 nm process in the 478-pin package will be referred
to as the “Celeron D processor,” or simply “the processor.”
Note: In this document, unless otherwise specified, the Intel^® Celeron^® D processor 3xx sequence refers
to Intel Celeron D processors 350, 345, 340, 335, 330, 325, and 320.
In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new
instructions that further extend the capabilities of Intel processor technology. These new
instructions are called Steaming SIMD Extensions 3 (SSE3).
The Celeron D processor’s Front Side Bus (FSB) uses a split-transaction, deferred reply protocol
like the Intel^® Pentium 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address
and data to improve performance by transferring data four times per bus clock (4X data transfer
rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times
per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X
data bus and 2X address bus provide a data bus bandwidth of up to 4.2 GB/s.
Intel will enable support components for the Celeron D processor including heatsink, heatsink
retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly
may be completed from the top of the baseboard and should not require any special tooling.
The processor includes an address bus powerdown capability that removes power from the address
and data pins when the FSB is not in use. This feature is always enabled on the processor.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front Side Bus (FSB)” refers to the interface between the processor and system core logic (a.k.a.
the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.
Datasheet
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