3XX Datasheet, PDF (23/82 Pages) Intel Corporation – Celeron D Processor

Electrical Specifications
2.11 Processor DC Specifications
The processor DC specifications in this section are defined at the processor core silicon and
not at the package pins unless noted otherwise. See Chapter 4 for the pin signal definitions and
signal pin assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The
DC specifications for these signals are listed in Table 2-10.
Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage
CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The
DC specifications for these signal groups are listed in Table 2-11 and Table 2-12.
Table 2-8 through Table 2-15 list the DC specifications for the Celeron D processor and are valid
only while meeting specifications for case temperature, clock frequency, and input voltages. Care
should be taken to read all notes associated with each parameter.
Table 2-8. Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit Notes
VID range
VID
1.250
—
1.400
V
1
V_CC
V_CC
See Table 2-9 and VID – I_CC(max)
Figure 2-2
* 1.45 mΩ
V
2,3,4
Processor
Number
Core Frequency
I_CC for processor with
multiple VID:
350
3.20 GHz
73
I_CC
345
3.06 GHz
73
340
2.93 GHz
—
—
73
A
5
335
2.80 GHz
73
330
2.66 GHz
73
325
2.53 GHz
73
320
2.40 GHz
73
I_CC Stop-Grant
350
3.20 GHz
40
345
3.06 GHz
40
I_SGNT
340
2.93 GHz
—
—
40
A
6,7
I_SLP
335
2.80 GHz
40
330
2.66 GHz
40
325
2.53 GHz
40
320
2.40 GHz
40
I_TCC
I_CC TCC active
I_{CC_VCCA}
I_CC for PLL pins
I_{CC_VCCIOPLL} I_CC for I/O PLL pin
—
—
—
—
—
—
I_CC
A
8
60
mA
9
60
mA
9
I_{CC_GTLREF} I_CC for GTLREF pins (all pins)
—
—
200
µA
I_{CC_VCCVID}/
VCCVIDLB
I_CC for VCCVID/VCCVIDLB
—
—
150
mA
9
NOTES:
1. Individual processor VID values may be calibrated during manufacturing such that two devices at the same
speed may have different VID settings.
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a differ-
ent voltage is required. See Section 2.4 and Table 2-2 for more information.
Datasheet
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