82562V Datasheet, PDF (5/42 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect

Networking Silicon — 82562V
Figure 2. 82562V PLC 10/100 Mbps Ethernet Solution
2.1.1
Reset/Synchronize Operations
The Reset/Synchronize signal used by the LAN Connect Interface is driven by the ICHx integrated
LAN device. It has two functions:
• Synchronize. When this pin is activated synchronously for only one LAN connect clock, it is
used for synchronization between the ICHx integrated LAN and PHY on LAN connect word
boundaries.
• Reset. When this pin is asserted beyond one LAN connect clock, the 82562V uses this signal
as a reset signal. To ensure a reset of the 82562V, the reset should remain active for at least 500
µs.
2.1.2
Reset Considerations
When the 82562V Reset signal (JRSTSYNC) is asserted for at least 500 µs, all internal circuits are
reset. The 82562V can also be reset by setting the MII register Reset bit equal to 1 (Register 0, bit
15).
The 82562V filters out JRSTSYNC pulses with a width of less than 200 ns to distinguish between
a reset and synchronize pulse. Again, the Reset signal should be longer than 500 µs to reset the
82562V.
Datasheet
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