82562V Datasheet, PDF (4/42 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect

82562V — Networking Silicon
2.0
82562V Architectural Overview
The 82562V PLC is a 3.3 V device in a 81-pin Mold Cap package. In normal operating mode, the
82562V incorporates all active circuitry required to interface with the Intel^® ICHx device with an
integrated 10/100 Mbps LAN controller. The 82562V supports a direct interface to all Media
Access Control (MAC) components that meet the Platform LAN connect interface specification.
Figure 1 shows a block diagram of the 82562V architecture.
RDN/RDP
TDN/TDP
Digital
Equalizer
Adaptation
Equalizer &
BLW correction
Digital Clock
Recovery (100)
CRS/Link 10
Detection
Digital Clock
Recovery (10)
Transmit DAC
10/100
Bias & Band-
Gap Voltage
Circuit
Clock
Generator
100Base-TX
PCS
10Base-T
PCS
Auto-
Negotiation
Control
Registers
Port LED
Drivers
LILED#
ACTLED#
SPDLED#
LAN
Connect
Interface
JRSTSYNC
JTXD[2:0]
3
3
JRXD[2:0]
JCLK
X1
Crystal
X2
25 MHz
Figure 1. 82562V PLC Block Diagram
2.1
LAN Connect Interface
The 82562V supports a LAN Connect Interface (LCI) as specified in the LCI Specification. The
LAN Connect is the I/O Control Hub 2 (ICH2) interface to the 82562V. The LCI uses an 8-pin
interface, which reduces the pin count from 15, for an Media Independent Interface (MII) PHY. In
addition, its signaling protocol provides greater functionality, such as dynamic power reduction,
from a PLC in comparison to a standard MII PHY.
Figure 2 shows how the 82562V can be used in a 10/100 Mbps ICHx design.
I_I//_OO _CC_oo_nn_trt_oro_l l_HH_ubub₄
LA(NICHC4o)nLtrAoNller
Controller
82562EZ
8^(P2^l5^a6^tf2^orV^mP^LL^AC^N
Connect
Device)
Transmit Differential Pair
(TDP/TDN)
Receive Differential Pair
(RDP/RDN)
System Bus Interface
2
Magnetics
Datasheet