82562V Datasheet, PDF (26/42 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect

82562V — Networking Silicon
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
Bit(s)
Name
15:0
Disconnect Event
Description
This field contains a 16-bit counter that increments for each
disconnect event. The counter stops when it is full and self-
clears on read
Default
--
R/W
RO
SC
Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions
Bit(s)
Name
15:0
Receive Error
Frame
Description
This field contains a 16-bit counter that increments once
per frame for any receive error condition (such as a symbol
error or premature end of frame) in that frame. The counter
stops when it is full and self-clears on read.
Default
--
R/W
RO
SC
Register 22: Receive Symbol Error Counter Bit Definitions
Bit(s)
Name
15:0
Symbol Error
Counter
Description
This field contains a 16-bit counter that increments for each
symbol error. The counter stops when it is full and self-
clears on read.
In a frame with a bad symbol, each sequential six bad
symbols count as one.
Default
--
R/W
RO
SC
Register 23: 100BASE-TX Receive Premature End of Frame Error Counter
Bit Definitions
Bit(s)
Name
15:0
Premature End of
Frame
Description
This field contains a 16-bit counter that increments for each
premature end of frame event. The counter stops when it is
full and self-clears on read.
Default
--
R/W
RO
SC
Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions
Bit(s)
Name
15:0
End of Frame
Counter
Description
This is a 16-bit counter that increments for each end of
frame event. The counter stops when it is full and self-
clears on read.
Default
--
R/W
RO
SC
Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions
Bit(s)
Name
15:0
Jabber Detect
Counter
Description
This is a 16-bit counter that increments for each jabber
detection event. The counter stops when it is full and self-
clears on read.
Default
--
R/W
RO
SC
24
Datasheet