82562V Datasheet, PDF (24/42 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect

82562V — Networking Silicon
6.3
6.3.1
6.3.2
MDI Registers 16 through 31
Register 16: PHY Status and Control Register Bit Definitions
Bit(s)
Name
Description
15:14
13
12
11
10
9
8
7
6:2
1
0
Reserved
Reduced Power
Down Disable
Reserved
Receive De-
Serializer In-Sync
Indication
100BASE-TX
Power-Down
10BASE-T Power-
Down
Polarity
Reserved
PHY Address
Speed
Duplex Mode
These bits are reserved and should be set to 00b.
This bit disables the automatic reduced power down.
0 = Enable automatic reduced power down
1 = Disable automatic reduced power down
This bit is reserved and should be set to 0b.
This bit indicates status of the 100BASE-TX Receive De-
Serializer In-Sync.
This bit indicates the power state of 100BASE-TX PHY
unit.
0 = Normal operation
1 = Power-down
This bit indicates the power state of 10BASE-T PHY unit.
0 = Normal operation
1 = Power-Down
This bit indicates 10BASE-T polarity.
0 = Normal polarity
1 = Reverse polarity
This bit is reserved and should be set to 0b.
These bits contain the sampled PHY address.
This bit indicates the Auto-Negotiation result.
0 = 10 Mbps
1 = 100 Mbps
This bit indicates the Auto-Negotiation result.
0 = Half-duplex
1 = Full-duplex
Default
00
1
R/W
RW
RW
0
RW
--
RO
1
RO
1
RO
--
RO
0
RO
--
RO
--
RO
--
RO
Register 17: PHY Unit Special Control Bit Definitions
Bit(s)
Name
Description
15
Scrambler By-pass 0 = Normal operations
1 = By-pass scrambler
14
By-pass 4B/5B
0 = Normal operation
1 = 4 bit to 5 bit by-pass
13
Force Transmit H- 0 = Normal operation
Pattern
1 = Force transmit H-pattern
12
Force 34 Transmit 0 = Normal operation
Pattern
1 = Force 34 transmit pattern
Default
0
R/W
RW
0
RW
0
RW
0
RW
22
Datasheet