82562V Datasheet, PDF (11/42 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect

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Networking Silicon — 82562V
82562V Signal Descriptions
Signal Type Definitions
Type
I
O
I/O
MLT
B
DPS
APS
Name
Description
Input
Input pin to the 82562V.
Output
Output pin from the 82562V.
Input/Output Multiplexed input and output pin to and from the 82562V.
Multi-level
analog I/O
Multi-level analog pin used for input and output.
Bias
Bias pin used for ground connection through a resistor or an external voltage reference.
Digital Power Digital power or ground pin for the 82562V.
Supply
Analog Power Analog power or ground pin for the 82562V.
Supply
Twisted Pair Ethernet (TPE) Pins
Pin Name
TDP
TDN
RDP
RDN
Pin
Number
Type
Description
B8
MLT Transmit Differential Pair. The transmit differential pair sends serial bit
B9
streams to the unshielded twisted pair (UTP) cable. The differential pair is a two-
level signal in 10BASE-T (Manchester) mode and a three-level signal in
100BASE-TX mode (MLT-3). These signals directly interface with the isolation
transformer.
D9
MLT Receive Differential Pair. The receive differential pair receive the serial bit
D8
stream from an unshielded twisted pair (UTP) cable. The differential pair is a
two-level signal in 10BASE-T mode (Manchester) or a three-level signal in
100BASE-TX mode (MLT-3). These signals directly interface with an isolation
transformer.
External Bias Pins
Pin Name
Pin
Number
Type
Description
RBIAS10
H7
B
Reference Bias Resistor (100 Mbps). This pin should be connected to a
pull-down resistor.^a
RBIAS100 G7
B
Reference Bias Resistor (10 Mbps). This pin should be connected to a pull-
down resistor.^a
a. Based on some board designs, RBIAS100 and RBIAS10 values may need to be increased/decreased to compensate for high/low MDI
transmit amplitude. See the 82562G/GT and 82562ET/EM LAN on Motherboard Design Guide for more information.
Datasheet
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