82562V Datasheet, PDF (21/42 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect

Networking Silicon — 82562V
6.1.2
Bit(s)
10
Name
Isolate
9
Restart Auto-
Negotiation
8
Duplex Mode
7
Collision Test
6:0
Reserved
Description
This bit allows the PHY to isolate the medium independent
interface. The PHY is disconnected from the LAN Connect
block on both the transmit and receive side.
0 = Normal operation
1 = Isolates internal medium independent interface
This bit restarts the Auto-Negotiation process and is self-
clearing.
0 = Normal operation
1 = Restart Auto-Negotiation process
This bit controls the duplex mode when Auto-Negotiation is
disabled. When Auto-Negotiation is enabled this bit is read
only and always equals 1b.
When the PHY is placed in Loopback mode, the behavior of
the PHY shall not be affected by the status of this bit.
0 = Half Duplex
1 = Full Duplex
This bit is not used in the 82562V and has a default value of 1b.
(If it is used in other devices, it forces a collision in response to
the assertion of the transmit enable signal.)
These bits are reserved and should be set to 0b.
Default R/W
0
RW
0
RW
SC
0
RW/
RO
1
RW
0
RW
Register 1: Status Register Bit Definitions
Bit(s)
Name
Description
15
Reserved
This bit is reserved and should be set to 0b.
14
100BASE-TX Full- This bit enables 100BASE-TX full-duplex operation and is
duplex
dependent on ADV10. If ADV10 is active, the default
value is 0.
0 = PHY unable to perform full-duplex 100BASE-TX
1 = PHY able to perform full-duplex 100BASE-TX
13
100 Mbps Half-
This bit enables 100BASE-TX half-duplex operation and is
duplex
dependent on ADV10. If ADV10 is active, the default
value is 0.
0 = PHY unable to perform half-duplex 100BASE-TX
1 = PHY able to perform half-duplex 100BASE-TX
12
10 Mbps Full-
This bit enables 10BASE-T full duplex operation.
duplex
0 = PHY unable to perform full-duplex 10BASE-T
1 = PHY able to perform full-duplex 10BASE-T
11
10 Mbps Half-
This bit enables 10BASE-T half-duplex operation.
duplex
0 = PHY unable to perform half-duplex 10BASE-T
1 = PHY able to perform half-duplex 10BASE-T
10:7
Reserved
These bits are reserved and should be set to 0b.
6
Management
This bit allows the 82562V to receive management frames
Frames Preamble with suppressed preamble.
Suppression
0 = PHY will not accept management frames with
preamble suppressed
1 = PHY will accept management frames with preamble
suppressed
Default
0
1
R/W
RO
RO
1
RO
1
RO
1
RO
0
RO
0
RO
Datasheet
19