82562V Datasheet, PDF (12/42 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect

82562V — Networking Silicon
4.4
Clock Pins
Pin Name
X1
X2
Pin
Number
Type
Description
H6
I
Crystal Input Clock. X1 and X2 can be driven by an external 25 MHz crystal of
30 PPM. Otherwise, X1 is driven by an external metal-oxide semiconductor
(MOS) level 25 MHz oscillator when X2 is left floating.
H5
O
Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz crystal
of 30 PPM.
4.5
Platform LAN Connect Interface Pins
Pin Name
JCLK
JRSTSYNC
JTXD[2:0]
JRXD[2:0]
Pin
Number
Type
Description
E2
O
E3
I
D1, F1, I
H9
C1, D2, O
D3
LAN Connect Clock. The LAN Connect Clock is driven by the 82562V on two
frequencies depending on operation speed. When the 82562V is in 100BASE-TX
mode, JCLK drives a 50 MHz clock. Otherwise, JCLK drives a 5 MHz clock for
10BASE-T. The JCLK does not stop during normal operation.
Reset/Synchronize. This is a multiplexed pin and is driven by the Media Access
Control (MAC) layer device. Its functions are:
• Reset. When this pin is asserted beyond one LAN Connect clock period, the
82562V uses this signal Reset. To ensure reset of the 82562V, the Reset
signal should remain active for at least 500 µs.
• Synchronize. When this pin is activated synchronously, for only one LAN
Connect clock period, it is used to synchronize the MAC and PHY on LAN
Connect word boundaries.
LAN Connect Transmit Data. The LAN Connect transmit pins are used to
transfer data from the MAC device to the 82562V. These pins are used to move
transmitted data and real time control and management data. They also transmit
out of band control data from the MAC to the PHY. The pins should be fully
synchronous to JCLK.
LAN Connect Receive Data. The LAN Connect receive pins are used to
transfer data from the 82562V to the MAC device. These pins are used to move
received data and real time control and management data. They also move out of
band control data from the PHY to the MAC. These pins are synchronous to
JCLK.
4.6
LED Pins
Pin Name
LILED#
ACTLED#
SPDLED#
Pin Number Type
Description
A4
O
Link Integrity LED. The LILED# signal has three logic modes. The LED configurations are
listed in Table 2, “LED Logic Functionality”.
B4
O
Activity LED. The LED is active low and the Activity LED signal indicates either receive or
transmit activity. When no activity is present, the LED is off. The Activity LED will flicker
when activity is present. The flicker rate depends on the activity load.
If Address Matching mode is enabled by the MAC, this pin will also indicate address match
events on previously received frames.
A5
O
Speed LED. The SPDLED# signal has three logic modes. The LED configurations are listed
in Table 2, “LED Logic Functionality”.
10
Datasheet