82562V Datasheet, PDF (20/42 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect

82562V — Networking Silicon
6.0
6.1
6.1.1
Platform LAN Connect Registers
The following sections describe PHY registers that are accessible through the LAN Connect
management frame protocol.
Acronyms mentioned in the registers are defined as follows:
SC: Self cleared.
RO: Read only.
RW: Read/Write.
E: EEPROM setting affects content.
LL: Latch low.
LH: Latch high.
Medium Dependent Interface (MDI) Registers 0 through 7
Register 0: Control Register Bit Definitions
Bit(s)
15
Name
Reset
14
Loopback
13
Speed Selection
12
Auto-Negotiation
Enable
11
Reduced Power
Down
Description
This bit sets the status and control register of the PHY to their
default states and is self-clearing. The PHY returns a value of
one until the reset process has completed and accepts a read or
write transaction.
0 = Normal operation
1 = PHY Reset
This bit enables loopback of transmit data nibbles to the
receive data path. The PHY receive circuitry is isolated from
the network.
Note that this may cause the descrambler to lose
synchronization and produce 560 ns of “dead time.”
Note also that the loopback configuration bit takes priority over
the Loopback MDI bit.
0 = Loopback disabled (normal operation)
1 = Loopback enabled
This bit is valid on read and controls speed when Auto-
Negotiation is disabled.
0 = 10 Mbps
1 = 100 Mbps
This bit enables Auto-Negotiation. Bits 13 and 8, Speed
Selection and Duplex Mode, respectively, are ignored when
Auto-Negotiation is enabled.
0 = Auto-Negotiation disabled
1 = Auto-Negotiation enabled
This bit sets the PHY into a low power mode.
0 = Power down disabled (normal operation)
1 = Power down enabled
Default R/W
0
RW
SC
0
RW
1
RW
1
RW
0
RW
18
Datasheet