82077AA Datasheet, PDF (41/62 Pages) Intel Corporation – CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

82077AA
Following a reset of the 82077AA the Configuration
Control Register (CCR) should be reinitialized for the
appropriate data rate An external reset via the RE-
SET pin will cause the data rate and write precom-
pensation values to default to 250 Kbps (10b) and
125 ns (000b) respectively Since the 125 ns write
precompensation value is optimal for the 5 and
3 disk drive environment most applications will
not require the value to be changed in the initializa-
tion sequence As a note a software reset issued via
the DOR or DSR will not affect the data rate or write
precompensation values But it is recommended as
a safe programming practice to always program the
data rate after a reset regardless of the type
Since polling is enabled after a reset of the
82077AA four SENSE INTERRUPT STATUS com-
mands need to be issued afterwards to clear the
status flags for each drive The flowchart in Figure 8-
3 illustrates how the software clears each of the four
interrupt status flags internally queued by the
82077AA It should be noted that although four
SENSE INTERRUPT STATUS commands are is-
sued the INT pin is only active until the first SENSE
INTERRUPT STATUS command is executed
290166 – 24
Figure 8-3 Initialization Flowchart
41