82077AA Datasheet, PDF (14/62 Pages) Intel Corporation – CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

82077AA
PHASE LOCK LOOP OVERVIEW
Figure 3-2 Data PLL
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Figure 3-2 shows the data PLL The reference PLL
has control over the loop gain by its influence on the
charge pump and the VCO In addition the reference
PLL controls the loop filter time constant As a result
the closed loop transfer function of the data PLL is
controlled and immune to the first order to environ-
mental factors and process variation
Systems with analog PLLs are often very sensitive to
noise In the design of this data separator many
steps were taken to avoid noise sensitivity problems
The analog section of the chip has a separate VSS
pin (AVSS) which should be connected externally to
a noise free ground This provides a clean basis for
VSS referenced signals In addition many analog cir-
cuit features were employed to make the overall sys-
tem as insensitive to noise as possible
3 2 1 JITTER TOLERANCE
The jitter immunity of the system is dominated by the
data PLL’s response to phase impulses This is mea-
sured as a percentage of the theoretical data win-
dow by dividing the maximum readable bit shift by a
bitcell distance For instance if the maximum al-
lowable bit shift is 300 ns for a 500 Kbps data
stream the jitter tolerance is 60% The graph in Fig-
ures 12-1 thru 12-4 and 13-1 thru 13-4 of the Data
Separator Characteristics sections illustrate the jitter
tolerance of the 82077AA across each frequency
range
3 2 2 LOCKTIME (tLOCK)
The lock or settling time of the data PLL is designed
to be 64 bit times This corresponds to 8 sync bytes
in the MFM mode This value assumes that the sync
field jitter is 5% the bit cell or less This level of jitter
should be easily achieved for a constant bit pattern
since intersymbol interference should be equal thus
nearly eliminating random bit shifting
3 2 3 CAPTURE RANGE
Capture Range is the maximum frequency range
over which the data separator will acquire phase
lock with the incoming RDDATA signal In a floppy
disk environment this frequency variation is com-
posed of two components drive motor speed error
and ISV Frequency is a factor which may determine
the maximum level of the ISV (Instantaneous Speed
Variation) component In general as frequency in-
creases the allowed magnitude of the ISV compo-
nent will decrease When determining the capture
range requirements the designer should take the
maximum amount of frequency error for the disk
drive and double it to account for media switching
between drives
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