82077AA Datasheet, PDF (38/62 Pages) Intel Corporation – CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

82077AA
Table 7-1 82077AA Register Support
82077AA
Register
8272A 82072 PC
XT PC
AT PS
2
Mod
30
SRA
XX
SRB
XX
DOR
X
X XX
MSR
XX X
X XX
DSR
X
Data (FIFO) X X X
X XX
DIR
X XX
CCR
X
X XX
CCR is emulated by DSR in an 82072 PC AT design
7 2 PS 2 vs AT vs Model 30 Mode
To maintain compatibility between PS 2 PC AT
and Model 30 environments the IDENT and MFM
pins are provided The 82077AA is placed into the
proper mode of operations upon Hardware RESET
with the appropriate settings of the IDENT and MFM
pins The proper settings of the IDENT and MFM
pins are described in IDENT’s pin description Differ-
ences between the three modes are described in
the following sections
7 2 1 PS 2 MODE
IDENT strapped low causes the polarity of DENSEL
to be active low for high (500 Kbps 1 Mbps) data
rates (typically used for 3 5 drives) This polalrity of
DENSEL assumes INVERT to be low A compre-
hensive description of DENSEL behavior is given in
Table 2-6
The DMAGATE bit in the Digital Output Register
(DOR) will not cause the DRQ or INT output signals
to tristate This maintains consistency with the oper-
ation of the floppy disk controller subsystem in the
PS 2 architecture
TC is an active low input signal that is internally qual-
ified by DACK being active low
7 2 2 PC AT MODE
IDENT strapped high causes the polarity of DENSEL
to be active high for high (500 Kbps 1 Mbps) data
rates (typically used for 5 25 drives) This polarity
of DENSEL assumes INVERT to be low A com-
prehensive description of DENSEL behavior is given
in Table 2-6
If the DMAGATE bit is written to a ‘‘0’’ in the Digital
Output Register (DOR) DRQ and INT will tristate If
DMAGATE is written to a ‘‘1’’ then DRQ and INT will
be driven appropriately by the 82077AA
TC is an active high input signal that is internally
qualified by DACK being active low
7 2 3 MODEL 30 MODE
IDENT strapped low causes the polarity of DENSEL
to be active low for high (500 Kbps 1 Mbps) data
rates (typically used for 3 5 drives) This polarity of
DENSEL assumes INVERT to be low A compre-
hensive description of DENSEL behavior is given in
Table 2-6
DMAGATE and TC function the same as in PC AT
Mode
7 3 Compatibility with the FIFO
The FIFO of the 82077AA is designed to be trans-
parent to non-FIFO disk controller software devel-
oped on the older generation 8272A standard Oper-
ation of the 82077AA FIFO can be broken down into
two tiers of compatibility For first tier compatibility
the FIFO is left in the default disabled condition
upon a ‘‘Hardware’’ reset (via pin 32) In this mode
the FIFO operates in a byte mode and provides
complete compability with non-FIFO based soft-
ware For second tier compatibility the FIFO is en-
abled via the CONFIGURE command When the
FIFO is enabled it will temporarily enter a byte mode
during the command and result phase of disk con-
troller operation This allows for compatible opera-
tion when interrogating the Main Status Register
(MSR) for the purpose of transferring a byte at a
time to or from the disk controller For normal disk
controller applications the system designer can still
take advantage of the FIFO for time critical data
transfers during the execution phase and not create
any conflicts with non-FIFO software during the
command or result phase
In some instances use of the FIFO in any form has
conflicted with certain specialized software An ex-
ample of a compatibility conflict using the FIFO is
with software that monitors the progress of a data
transfer during the execution phase If the software
assumed the disk controller was operating in a sin-
gle byte mode and counted the number of bytes
transferred to or from the disk controller to trigger
some time dependent event on the disk media (i e
head position over a specific data field) the same
software will not have an identical time relationship if
the FIFO is enabled This is because the FIFO al-
lows data to be queued up and then burst trans-
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