82077AA Datasheet, PDF (4/62 Pages) Intel Corporation – CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

82077AA
Table 1 82077AA Pin Description
Symbol Pin I O
Description
HOST INTERFACE
RESET 32 I RESET A high level places the 82077AA in a known idle state All registers are cleared
except those set by the Specify command
CS
6 I CHIP SELECT Decodes base address range and qualifies RD and WR inputs
A0
7 I ADDRESS Selects one of the host interface registers
A1
8
A2 A1 A0
A2
10
Register
0 0 0 R Status Register A
0 0 1 R Status Register B
0 1 0 R W Digital Output Register
0 1 1 R W Tape Drive Register
1 0 0 R Main Status Register
1 0 0 W Data Rate Select Register
1 0 1 R W Data (FIFO)
110
Reserved
1 1 1 R Digital Input Register
1 1 1 W Configuration Control Register
DB0
11 I O DATA BUS Data bus with 12 mA drive
DB1
13
DB2
14
DB3
15
DB4
17
DB5
19
DB6
20
DB7
22
RD
4 I READ Control signal
WR
5 I WRITE Control signal
DRQ
24 O DMA REQUEST Requests service from a DMA controller Normally active high but
goes to high impedance in AT and Model 30 modes when the appropriate bit is set in the
DOR
DACK 3 I DMA ACKNOWLEDGE Control input that qualifies the RD WR inputs in DMA cycles
Normally active low but is disabled in AT and Model 30 modes when the appropriate bit
is set in the DOR
TC
25 I TERMINAL COUNT Control line from a DMA controller that terminates the current disk
transfer TC is accepted only while DACK is active This input is active high in the AT
and Model 30 modes and active low in the PS 2 mode
INT
23 O INTERRUPT Signals a data transfer in non-DMA mode and when status is valid
Normally active high but goes to high impedance in AT and Model 30 modes when the
appropriate bit is set in the DOR
X1
33
CRYSTAL 1 2 Connection for a 24 MHz fundamental mode parallel resonant crystal X1
X2
34
may be driven with a MOS level clock and X2 would be left unconnected
4