82077AA Datasheet, PDF (35/62 Pages) Intel Corporation – CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

82077AA
With the old implementation the user must properly
program both the PERPENDICULAR MODE com-
mand and write pre-compensation value before ac-
cessing either a Conventional or Perpendicular
drive These programmed values apply to all drives
(D0–D3) which the 82077AA may access It should
also be noted that any form of RESET ‘‘Hardware’’
or ‘‘Software’’ will configure the PERPENDICULAR
MODE command for Conventional mode (GAP and
WGATE ^e ‘‘0’’)
With the enhanced implementation both the GAP
and WGATE bits have the same affects as the old
implementation except for when they are both pro-
grammed for value of ‘‘0’’ (Conventional mode) For
the case when both GAP and WGATE equal ‘‘0’’ the
PERPENDICULAR MODE command will have the
following effect on the 82077AA 1) If any of the new
bits D0 D1 D2 and D3 are programmed to ‘‘1’’ the
corresponding drive will automatically be pro-
grammed for Perpendicular mode (ie GAP2 being
written during a write operation the programmed
Data Rate will determine the length of GAP2 ) and
data will be written with 0 ns write pre-compensa-
tion 2) any of the new bits (D0–D3) that are pro-
grammed for ‘‘0’’ the designated drive will be pro-
grammed for Conventional Mode and data will be
written with the currently programmed write pre-
compensation value 3) Bits D0 D1 D2 and D3 can
only be over written when the OW bit is written as a
‘‘1’’ The status of these bits can be determined by
interpreting the eighth result byte of the enhanced
DUMPREG Command (See Section 5 3 3) (Note if
either the GAP or WGATE bit is a ‘‘1’’ then bits D0 –
D3 are ignored )
‘‘Software’’ and ‘‘Hardware’’ RESET will have the
following effects on the enhanced PERPENDICU-
LAR MODE command
1) ‘‘Software’’ RESETs (Reset via DOR or DSR reg-
isters) will only clear GAP and WGATE bits to
‘‘0’’ D3 D2 D1 and D0 will retain their previously
programmed values
2) ‘‘Hardware’’ RESETs (Reset via pin 32) will clear
all bits (GAP Wgate D0 D1 D2 and D3) to ‘‘0’’
(All Drives Conventional Mode)
5 3 2 LOCK
In order to protect a system with long DMA latencies
against older application software packages that
can disable the 82077AA’s FIFO the following LOCK
Command has been added to the 82077AA’s com-
mand set Note This command should only be
used by the system’s FDC routines and ISVs (Inde-
pendent Software Vendors) should refrain from us-
ing it If an ISV’s application calls for having the
82077AA FIFO disabled a CONFIGURE Command
should be used to toggle the EFIFO (Enable FIFO)
bit ISV can determine the value of the LOCK bit by
interpreting the eighth result byte of an DUMPREG
Command (See Section 5 3 3)
The LOCK command defines whether EFIFO
FIFOTHR and PRETRK parameters of the CON-
FIGURE command can be RESET by the DOR and
DSR registers When the LOCK bit is set to a ‘‘1’’ all
subsequent ‘‘software’’ RESETs by the DOR and
DSR registers will not change the previously set pa-
rameter values in the CONFIGURE command When
the LOCK bit is set to a ‘‘0’’ ‘‘software’’ RESETs by
the DOR or DSR registers will return these parame-
ters to their default values (See Section 5 2 7) All
‘‘hardware’’ Resets by pin 32 will set the LOCK bit to
a ‘‘0’’ value and will return EFIFO FIFOTHR and
PRETRK to their default values A Status byte is re-
turned immediately after issuing the command byte
This Status byte reflects the value of the Lock bit set
by the command byte (Note No interrupts are gen-
erated at the end of this command )
5 3 3 ENHANCED DUMPREG COMMAND
To accommodate the new LOCK command and en-
hanced PERPENDICULAR MODE command the
eighth result byte of DUMPREG command has been
modified in the following manner
Phase R W
D7
D6
Result R
R LOCK
0
Data Bus
D5
D4
D3
D2
DUMPREG
Eighth Result Byte
Undefined
D3
D2
D1
D0
Remarks
D1
D0
GAP
Old
WGATE ^Enhanced
NOTES
1 Data bit 7 reflects the status of the new LOCK bit set by the LOCK Command
2 Data Bits D0–D5 reflect the status for bits D3 D2 D1 D0 GAP and WGATE set by the PERPENDICULAR MODE
Command
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