82077AA Datasheet, PDF (16/62 Pages) Intel Corporation – CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

82077AA
the command unless an illegal command condition
is detected After the last parameter byte is re-
ceived RQM remains ‘‘0’’ and the 82077AA auto-
matically enters the next phase as defined by the
command definition
The FIFO is disabled during the command phase to
retain compatibility with the 8272A and to provide
for the proper handling of the ‘‘Invalid Command’’
condition
4 2 Execution Phase
All data transfers to or from the 82077AA occur dur-
ing the execution phase which can proceed in DMA
or non-DMA mode as indicated in the SPECIFY
command
Each data byte is transferred by an INT or DRQ de-
pending on the DMA mode The CONFIGURE com-
mand can enable the FIFO and set the FIFO thresh-
old value
The following paragraphs detail the operation of the
FIFO flow control In these descriptions ^kthresh-
old^l is defined as the number of bytes available to
the 82077AA when service is requested from the
host and ranges from 1 to 16 The parameter FI-
FOTHR which the user programs is one less and
ranges from 0 to 15
A low threshold value (i e 2) results in longer peri-
ods of time between service requests but requires
faster servicing of the request for both read and
write cases The host reads (writes) from (to) the
FIFO until empty (full) then the transfer request
goes inactive The host must be very responsive to
the service request This is the desired case for use
with a ‘‘fast’’ system
A high value of threshold (i e 12) is used with a
‘‘sluggish’’ system by affording a long latency period
after a service request but results in more frequent
service requests
4 2 1 NON-DMA MODE TRANSFERS FROM THE
FIFO TO THE HOST
The INT pin and RQM bits in the Main Status Regis-
ter are activated when the FIFO contains (16 –
k_thresholdl_{) bytes or the last bytes of a full sector}
transfer have been placed in the FIFO The INT pin
can be used for interrupt driven systems and RQM
can be used for polled sytems The host must re-
spond to the request by reading data from the FIFO
This process is repeated until the last byte is trans-
ferred out of the FIFO The 82077AA will deactivate
the INT pin and RQM bit when the FIFO becomes
empty
4 2 2 NON-DMA MODE TRANSFERS FROM THE
HOST TO THE FIFO
The INT pin and RQM bit in the Main Status Register
are activated upon entering the execution phase of
data transfer commands The host must respond to
the request by writing data into the FIFO The INT
pin and RQM bit remain true until the FIFO becomes
full They are set true again when the FIFO has
k_thresholdl _{bytes remaining in the FIFO The INT}
pin will also be deactivated if TC and DACK both
go inactive The 82077AA enters the result phase
after the last byte is taken by the 82077AA from the
FIFO (i e FIFO empty condition)
4 2 3 DMA MODE TRANSFERS FROM THE FIFO
TO THE HOST
The 82077AA activates the DRQ pin when the FIFO
contains (16 – ^kthreshold^l) bytes or the last byte
of a full sector transfer has been placed in the FIFO
The DMA controller must respond to the request by
reading data from the FIFO The 82077AA will deac-
tivate the DRQ pin when the FIFO becomes empty
DRQ goes inactive after DACK goes active for the
last byte of a data transfer (or on the active edge of
RD on the last byte if no edge is present on
DACK ) A data underrun may occur if DRQ is not
removed in time to prevent an unwanted cycle
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