82077AA Datasheet, PDF (11/62 Pages) Intel Corporation – CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

82077AA
COMMAND BUSY This bit is set to a one when a
command is in progress This bit will go active after
the command byte has been accepted and goes in-
active at the end of the results phase If there is no
result phase (SEEK RECALIBRATE commands)
this bit is returned to a 0 after the last command
byte
DRV x BUSY These bits are set to ones when a
drive is in the seek portion of a command including
seeks and recalibrates
2 1 7 FIFO (DATA)
All command parameter information and disk data
transfers go through the FIFO The FIFO is 16 bytes
in size and has programmable threshold values
Data transfers are governed by the RQM and DIO
bits in the Main Status Register
The FIFO defaults to an 8272A compatible mode
after a ‘‘Hardware’’ reset (Reset via pin 32) ‘‘Soft-
ware’’ Resets (Reset via DOR or DSR register) can
also place the 82077AA into 8272A compatible
mode if the LOCK bit is set to ‘‘0’’ (See section 5 3 2
for the definition of the LOCK bit) This maintains
PC-AT hardware compatibility The default values
can be changed through the CONFIGURE com-
mand (enable full FIFO operation with threshold
control) The advantage of the FIFO is that it allows
the system a larger DMA latency without causing a
disk error Table 2 5 gives several examples of the
delays with a FIFO The data is based upon the fol-
lowing formula
1
Threshold c
c 8 b 1 5 ms e DELAY
DATA RATE
Table 2-5 FIFO Service Delay
FIFO Threshold Maximum Delay to Servicing
Examples
at 1 Mbps Data Rate
1 byte
2 bytes
8 bytes
15 bytes
1 ^c 8 ms ^b 1 5 ms ^e 6 5 ms
2 ^c 8 ms ^b 1 5 ms ^e 14 5 ms
8 ^c 8 ms ^b 1 5 ms ^e 62 5 ms
15 ^c 8 ms ^b 1 5 ms ^e 118 5 ms
FIFO Threshold Maximum Delay to Servicing
Examples
at 500 Kbps Data Rate
1 byte
2 bytes
8 bytes
15 bytes
1 ^c 16 ms ^b 1 5 ms ^e 14 5 ms
2 ^c 16 ms ^b 1 5 ms ^e 30 5 ms
8 ^c 16 ms ^b 1 5 ms ^e 126 5 ms
15 ^c 16 ms ^b 1 5 ms ^e 238 5 ms
At the start of a command the FIFO action is always
disabled and command parameters must be sent
based upon the RQM and DIO bit settings As the
82077AA enters the command execution phase it
clears the FIFO of any data to ensure that invalid
data is not transferred
An overrun or underrun will terminate the current
command and the transfer of data Disk writes will
complete the current sector by generating a 00 pat-
tern and valid CRC
2 1 8a DIGITAL INPUT REGISTER
(DIR PC-AT MODE)
This register is read only in all modes In PC-AT
mode only bit 7 is driven all other bits remain tristat-
ed
7
6
5
4
3
2
1
0
DSK
CHG
DSKCHG monitors the pin of the same name and
reflects the opposite value seen on the disk cable
regardless of the value of INVERT
2 1 8b DIGITAL INPUT REGISTER
(DIR PS 2 MODE)
7
6
5
4
3
2
1
0
DSK
DRATE DRATE HIGH
1
1
1
1
CHG
SEL1 SEL0 DENS
The following is changed in PS 2 Mode Bits 6 5 4
and 3 return a value of ‘‘1’’ and the DRATE SEL1-0
return the value of the current data rate selected
(see Table 2-4 for values)
HIGH DENS is low whenever the 500 Kbps or
1 Mbps data rates are selected This bit is indepen-
dent of the effects of the IDENT and INVERT pins
Table 2-6 shows the state of the DENSEL pin when
INVERT is low
Table 2-6 DENSEL Encoding
Data Rate
IDENT
DENSEL
1 Mbps
0
0
1
1
500 Kbps
0
0
1
1
300 Kbps
0
1
1
0
250 Kbps
0
1
1
0
After (‘‘Hardware’’) Chip Reset
11