82077AA Datasheet, PDF (13/62 Pages) Intel Corporation – CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

82077AA
3 1 Cable Interface
The INVERT pin selects between using the internal
buffers on the 82077AA or user supplied inverting
buffers INVERT pulled to V_CC disables the internal
buffers pulled to ground will enable them There is
no need to use external buffers with the 82077AA in
typical PC applications
The polarity of the DENSEL pin is controlled through
the IDENT pin after hardware reset For 5 25
drives a high on DENSEL tells the drive that either
the 500 Kbps or 1 Mbps data rate is selected For
some 3 5 drives the polarity of DENSEL changes
to a low for high data rates See Table 2-6 DENSEL
Encoding for IDENT pin settings
Additionally the two types of drives have different
electrical interfaces Generally the 5 25 drive uses
open collector drivers and the 3 5 drives (as used
on PS 2) use totem-pole drivers The output buffers
on the 82077AA do not change between open col-
lector or totem-pole they are always totem-pole For
design information on interfacing 5 25 and 3 5
drives to a single 82077AA refer to Section 9
3 2 Data Separator
The function of the data separator is to lock onto the
incoming serial read data When lock is achieved the
serial front end logic of the chip is provided with a
clock which is synchronized to the read data The
synchronized clock called Data Window is used to
internally sample the serial data One state of Data
Window is used to sample the data portion of the bit
cell and the alternate state samples the clock por-
tion Serial to parallel conversion logic separates the
read data into clock and data bytes
To support reliable disk tape reads the data separa-
tor must track fluctuations in the read data frequen-
cy Frequency errors primarily arise from two sourc-
es motor rotation speed variation and instanta-
neous speed variation (ISV) A second condition
and one that opposes the ability to track frequency
shifts is the response to bit jitter
The internal data separator consists of two analog
phase lock loops (PLLs) as shown in Figure 3-1 The
two PLLs are referred to as the reference PLL and
the data PLL The reference PLL (the master PLL) is
used to bias the data PLL (the slave PLL) The refer-
ence PLL adjusts the data PLL’s operating point as a
function of process junction temperature and supply
voltage Using this architecture it was possible to
eliminate the need for external trim components
Figure 3-1 Data Separator Block Diagram
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