82077AA Datasheet, PDF (31/62 Pages) Intel Corporation – CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

82077AA
Note that if implied seek is not enabled the read and
write commands should be preceded by
1) SEEK command
Step to the proper track
2) SENSE INTERRUPT Terminate the Seek
STATUS command command
3) READ ID
Verify head is on
proper track
4) Issue READ WRITE
command
The SEEK command does not have a result phase
Therefore it is highly recommended that the SENSE
INTERRUPT STATUS Command be issued after the
SEEK command to terminate it and to provide verifi-
cation of the head position (PCN) The H bit (Head
Address) in ST0 will always return a ‘‘0’’ When exit-
ing POWERDOWN mode the 82077AA clears the
PCN value and the status information to zero Prior
to issuing the POWERDOWN command it is highly
recommended that the user service all pending in-
terrupts through the SENSE INTERRUPT STATUS
command
5 2 4 SENSE INTERRUPT STATUS
An interrupt signal on INT pin is generated by the
82077AA for one of the following reasons
1 Upon entering the Result Phase of
a READ DATA Command
b READ TRACK Command
c READ ID Command
d READ DELETED DATA Command
e WRITE DATA Command
f FORMAT TRACK Command
g WRITE DELETED DATA Command
h VERIFY Command
2 End of SEEK RELATIVE SEEK or RECALI-
BRATE Command
3 82077AA requires a data transfer during the exe-
cution phase in the non-DMA Mode
The SENSE INTERRUPT STATUS command resets
the interrupt signal and via the IC code and SE bit of
Status Register 0 identifies the cause of the inter-
rupt If a SENSE INTERRUPT STATUS command is
issued when no active interrupt condition is present
the status register ST0 will return a value of 80H
(invalid command)
Table 5-9 Interrupt Identification
SE IC
Interrupt Due To
0 11 Polling
1 00 Normal Termination of SEEK or
RECALIBRATE command
1 01 Abnormal Termination of SEEK or
RECALIBRATE command
The SEEK RELATIVE SEEK and the RECALI-
BRATE commands have no result phase SENSE
INTERRUPT STATUS command must be issued im-
mediately after these commands to terminate them
and to provide verification of the head position
(PCN) The H (Head Address) bit in ST0 will always
return a ‘‘0’’ If a SENSE INTERRUPT STATUS is
not issued the drive will continue to be BUSY and
may effect the operation of the next command
5 2 5 SENSE DRIVE STATUS
SENSE DRIVE STATUS obtains drive status infor-
mation It has no execution phase and goes directly
to the result phase from the command phase
STATUS REGISTER 3 contains the drive status in-
formation
5 2 6 SPECIFY
The SPECIFY command sets the initial values for
each of the three internal timers The HUT (Head
Unload Time) defines the time from the end of the
execution phase of one of the read write commands
to the head unload state The SRT (Step Rate Time)
defines the time interval between adjacent step
pulses Note that the spacing between the first and
second step pulses may be shorter than the remain-
ing step pulses The HLT (Head Load Time) defines
the time between the Head Load signal goes high
and the read write operation starts The values
change with the data rate speed selection and are
documented in Table 5-10
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