IA186XL Datasheet, PDF (69/75 Pages) InnovASIC, Inc – 16-Bit Microcontroller

IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
8. Errata
The following errata are associated with the IA186XL/IA188XL. A workaround to the identified
problem has been provided where possible.
8.1 Summary
Table 24 presents a summary of errata.
Table 24. Summary of Errata
Errata
No.
1
Problem
Pin LOCK_n does not have an internal pullup and
will float during reset and bus hold.
When the timer compare register for any of the
2 timers is set to x0000, the max count is xFFFF
instead of x10000 as in the OEM part.
Ver. 0
Exists
Ver. 1
Exists
Ver. 2
Exists
Exists Fixed Fixed
When using external interrupts IRQ0 or IRQ1 in
3 Cascade Mode, the acknowledge signal on INTA0
or INTA1 may be lost or truncated.
Exists
4
Memory->Memory moves interrupted by two DMA
cycles can corrupt data.
Exists
5
Bit 15 of RELREG (offset 0xFE) behaves
differently than Intel device.
Exists
6
Enhanced mode makes bit 15 of RELREG (offset
0xFE) read-only.
7 Sbus deasserts on the wrong edge of CLKOUT.
8
Timer2 count register must be written to enable
counting.
9
Non-maskable interrupt (NMI) can be pre-empted
by maskable interrupt.
10 DMA can hang.
Exists
Exists
Exists
Exists
Exists
Fixed Fixed
Fixed Fixed
Fixed Fixed
Fixed
Fixed
Exists
Exists
Exists
Fixed
Fixed
Fixed
Fixed
Fixed
®
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