IA186XL Datasheet, PDF (28/75 Pages) InnovASIC, Inc – 16-Bit Microcontroller

IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 7. IA186XL Pin/Signal Descriptions (Continued)
Signal
lcs_n
lock_n
Name
lcs_n
lock_n
Pin
PLCC
33
PQFP
46
48
28
LQFP
63
45
Description
lower chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
lock. Output. Active Low. When asserted
(low), this signal indicates that the bus cycle in
progress cannot be interrupted. While lock_n
is active, the IA186XL will not service bus
requests such as HOLD.
mcs0_n mcs0_n/pereq 38
mcs1_n mcs1_n/error_n 37
mcs2_n
mcs2_n
36
mcs3_n mcs3_n/nps_n 35
n.c.
n.c.
NA
nmi
nmi
46
nps_n mcs3_n/nps_n 35
pcs0_n
pcs0_n
25
pcs1_n
pcs1_n
27
pcs2_n
pcs2_n
28
pcs3_n
pcs3_n
29
pcs4_n
pcs4_n
30
pcs5_n pcs5_n/a1
31
pcs6_n pcs6_n/a2
32
pereq mcs0_n/pereq 38
39
40
41
42
2, 11,
14, 15,
24, 43,
44, 62,
63
30
42
54
52
51
50
49
48
47
39
57
58
59
60
4, 25,
35, 55,
72
When resin_n is active, this pin is weakly held
high and must not be driven low.
mid-range memory chip select. Output.
not connected.
47 non-maskable interrupt. Input. Active High.
When the nmi signal is asserted (high) it
causes a Type 2 interrupt.
60 numeric processor select
71 peripheral chip select signals 0–6. Output.
69
68
67
66
65
64
57 numerics coprocessor external request.
Input. Active High. When asserted (high), this
signal indicates that a data transfer between
an Intel 80C187 Numerics Coprocessor and
the CPU is pending.
®
IA211080711-09
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