IA186XL Datasheet, PDF (30/75 Pages) InnovASIC, Inc – 16-Bit Microcontroller

IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 7. IA186XL Pin/Signal Descriptions (Continued)
Signal
test_n
tmr in 0
tmr in 1
tmr out 0
tmr out 1
ucs_n
v_cc
v_ss
wr_n
x1
x2
Name
test_n/busy
tmr in 0
tmr in 1
tmr out 0
tmr out 1
ucs_n
v_cc
v_ss
wr_n/qs1
x1
x2
Pin
PLCC
47
20
21
22
23
34
9, 43
26,
60
63
59
58
PQFP
29
59
58
57
56
45
33, 34,
72, 73
12, 13,
53
8
16
17
LQFP
46
77
76
75
74
62
10, 11,
20, 50,
51, 61
30, 31,
41, 70,
80
27
32
33
Description
test. Input. Active Low. When the test_n
input is high (i.e., not asserted), it causes the
IA186XL to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
timer 0 input. Input. Depending on the Timer
Mode programmed for Timer 0, this input is
used either as clock input or a control signal.
timer 1 input. Input. Depending on the Timer
Mode programmed for Timer 1, this input is
used either as clock input or a control signal.
timer 0 output. Output. Depending on the
Timer Mode programmed for Timer 0, this
output can provide a single pulse or a
repetitive waveform.
timer 1 output. Output. Depending on the
Timer Mode programmed for Timer 1, this
output can provide a single clock or a
repetitive waveform.
upper chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
Power (V_CC). This pin provides power for the
IA186XL device. It must be connected to a
+5V DC power source.
Ground (V_SS). This pin provides the digital
ground (0V) for the IA186XL. It must be
connected to a V_SS board plane.
write. Output. Active Low. When asserted
(low), wr_n indicates that data available on
the data bus are to be latched into the
accessed memory or I/O device.
x1 and x2 are inputs for the crystal
®
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