IA186XL Datasheet, PDF (35/75 Pages) InnovASIC, Inc – 16-Bit Microcontroller

IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 8. IA188XL Pin/Signal Descriptions (Continued)
Signal
res_n
reset
rfsh_n
s0_n
s1_n
s2_n
Name
res_n
reset
rfsh_n
s0_n
s1_n
s2_n
Pin
PLCC
24
PQFP
55
57
18
64
7
52
23
53
22
54
21
LQFP
73
34
26
40
39
38
Description
res_n. Input. Forces the processor to
terminate its present activity, reset the internal
logic, and enter a dormant state until res_n
goes high.
reset is an output signal indicating the CPU is
being reset. It can be used as a system reset.
refresh. Output. rfsh_n is asserted low to
indicate a refresh bus cycle.
status [2:0]_n are outputs. During a bus cycle
the status (i.e., type) of cycle is encoded on
these lines as follows:
s2_n s1_n s0_n Bus Cycle Status
s3
a16/s3
68
3
s4
a17/s4
67
4
s5
a18/s5
66
5
s6
a19/s6
65
6
srdy
srdy
49
27
test_n test_n/busy
47
29
tmr in 0
tmr in 0
tmr in 1
tmr in 1
20
59
21
58
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 Processor HALT
1 0 0 Queue Instruction Fetch
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 No Bus Activity
21 status [6:3] are outputs.
22
23 ^{Bus Cycle A19/s6 A18/s5 A17/s4 A16/s3}
24
T₁
A19 A18 A17 A16
T₂
N
0
0
0
T₃
N
0
0
0
T_w
N
0
0
0
T₄
N
0
0
0
____________
N = 0 for CPU bus cycle.
N = 1 for DMA or refresh cycle.
44 synchronous ready. Input.
46 test. Input. Active Low. When the test_n
input is high (i.e., not asserted), it causes the
IA188XL to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
77 timer 0 input. Input. Depending on the Timer
Mode programmed for Timer 0, this input is
used either as clock input or a control signal.
76 timer 1 input. Input. Depending on the Timer
Mode programmed for Timer 1, this input is
used either as clock input or a control signal.
®
IA211080711-09
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