IA186XL Datasheet, PDF (29/75 Pages) InnovASIC, Inc – 16-Bit Microcontroller

IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 7. IA186XL Pin/Signal Descriptions (Continued)
Signal
qs0
qs1
Name
ale/qs0
wr_n/qs1
Pin
PLCC
61
63
PQFP
10
8
qsmd_n rd_n/qsmd_n 62
9
rd_n
rd_n/qsmd_n 62
9
res_n
res_n
24
55
reset
s0_n
s1_n
s2_n
reset
s0_n
s1_n
s2_n
57
18
52
23
53
22
54
21
s3
a16/s3
68
3
s4
a17/s4
67
4
s5
a18/s5
66
5
s6
a19/s6
65
6
srdy
srdy
49
27
LQFP
29
27
28
28
73
34
40
39
38
Description
queue status 0, queue status 1. Output.
QS1 QS0
0
0 No Queue operations
0
1 First byte of opcode pulled from
Queue
1
1 Additional bytes pulled from
Queue
1
0 Queue is flushed
queue status mode. Input. Sampled at reset.
read. output. Active Low. When asserted
(low), rd_n indicates that the accessed
memory or I/O device must drive data from the
location being accessed onto the data bus.
res_n. Input. Forces the processor to
terminate present activity, reset the internal
logic, and enter a dormant state until res_n
goes high.
reset is an output signal indicating the CPU is
being reset. It can be used as a system reset.
status [2:0]_n are outputs. During a bus
cycle, the status (i.e., type) of cycle is encoded
on these lines as follows:
s2_n s1_n s0_n Bus Cycle Status
00
0 Interrupt Acknowledge
00
1 Read I/O
01
0 Write I/O
01
1 Processor HALT
10
0 Queue Instruction Fetch
10
1 Read Memory
11
0 Write Memory
11
1 No Bus Activity
21 status [6:3] are Outputs.
22
23 ^{Bus Cycle A19/s6 A18/s5 A17/s4 A16/s3}
24
T₁
A19 A18 A17 A16
T₂
N
0
0
0
T₃
N
0
0
0
T_w
N
0
0
0
T₄
N
0
0
0
____________
N = 0 for CPU bus cycle.
N = 1 for DMA or refresh cycle.
44 synchronous ready. Input.
®
IA211080711-09
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