IA186XL Datasheet, PDF (26/75 Pages) InnovASIC, Inc – 16-Bit Microcontroller

IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 7. IA186XL Pin/Signal Descriptions (Continued)
Signal
ale
ardy
bhe_n
Name
ale/qs0
ardy
bhe_n
Pin
PLCC
61
PQFP
10
55
20
64
7
LQFP
29
37
26
Description
address latch enable. Output. Active High.
This signal is used to latch valid address
information on the falling edge of ale during
the address portion of a bus cycle.
asynchronous ready. Input. Indicates to the
processor the addressed memory space or i/o
device will complete the transfer.
byte high enable. Output. Active Low. When
bhe_n is asserted (low), it indicates that the
bus cycle in progress is transferring data over
the upper half of the data bus.
Additionally, bhe_n and ad0 encode the
following bus information:
busy
clkout
den_n
drq0
drq1
test_n/busy
clkout
den_n
drq0
drq1
®
ad0 bhe_n Bus Status
0
0 Word Transfer
0
1 Even Byte Transfer
1
0 Odd Byte Transfer
1
1 Refresh Operation
(Enhanced Mode)
47
29
56
19
39
38
18
61
19
60
Note: bhe_n is used as refresh_n in the
IA188XL.
46 busy. Input. Active High. Used in Enhanced
Mode. When the busy input is asserted, it
causes the IA186XL to suspend operation
during the execution of the Intel 80C187
Numerics Coprocessor instructions.
Operation resumes when the pin is sampled
low.
36 clock output. Output. The clkout pin
provides a timing reference for inputs and
outputs of the IA186XL. This clock output is
one-half the input clock (clkin) frequency.
The clkout signal has a 50% duty cycle,
transitioning every falling edge of clkin.
56 data enable. Output. Active Low. This signal
is used to enable bidirectional transceivers in
a buffered system. The den_n signal is
asserted (low) only when data are to be
transferred on the bus.
79 dma request 0 or 1. Input. Asserted high by
78 ^{an external device to request DMA Channel 0}
or 1 to perform a transfer. These signals are
level-triggered and internally synchronized.
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