IA82527 Datasheet, PDF (37/45 Pages) InnovASIC, Inc – Serial Communications Controller CAN Protocol

IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
Table 11. Mode 3 Synchronous Operation Timing
Symbol
1/t_XTAL
1/t_SCLK
1/t_MCLK
t_EHDV
t_ELDH
t_ELDZ
t_ELDV
t_AVEH
t_ELAV
t_CVEH
t_ELCV
t_DVEL
t_EHEL
t_AVAV
t_AVCL
t_CHAI
t_COPD
t_CHCL
Parameter
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
e High to Data Valid
(for High-Speed Registers 02H, 04H,
and 5H)
e High to Data Valid
(for Low-Speed Registers)
Read Cycle without Previous Write
e High to Data Valid
(for Low-Speed Registers)
Read Cycle with Previous Write
Data Hold after e Low for a Read Cycle
Data Float after e Low
Data Hold after e Low for a Write Cycle
Address and r-w_n to e Setup
Address and r-w_n Valid after e Falls
cs_n Valid to e High
cs_n Valid after e Low
Data Setup to e Low
e Active Width
Start of a Write Cycle after a Previous
Write Access
Address or r-w_n to cs_n Low Setup
cs_n High Address Invalid
clkout Period
(CD_V is the value loaded in the
CLKOUT Register representing the
clkout divisor.)
clkout High Period
(CD_V is the value loaded in the
CLKOUT Register representing the
clkout divisor.)
Minimum
8 MHz
4 MHz
2 MHz
—
Maximum
16 MHz
10 MHz
8 MHz
55 ns
—
1.5 t_mclk + 100 ns
—
5 ns
—
15 ns
25 ns
15 ns
0 ns
0 ns
55 ns
100 ns
2 t_mclk
3 ns
7 ns
3.5 t_mclk + 100 ns
—
35 ns
—
—
—
—
—
—
—
—
—
—
(CD_V + 1) * t_osc
(CDV + 1) * ½ tosc – 10 (CDV + 1) * ½ tosc + 15
Copyright  2007
©
EN21070504-00
Page 37 of 45
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