IA82527 Datasheet, PDF (22/45 Pages) InnovASIC, Inc – Serial Communications Controller CAN Protocol

IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
4.1.1 CAN Controller
The CAN Controller block of the IA82527 supports the interface to the CAN Bus via the rx0, rx1,
tx0, and tx1 lines. The CAN Controller manages the transceiver logic, error management logic,
and the message objects, controlling the data stream between the RAM (parallel data) and the
CAN Bus (serial data).
4.1.2 RAM
The RAM block of the IA82527 provides the interface buffer between the system CPU and the
CAN Bus. The IA82527 RAM provides storage for 15 message objects of 8-byte data length.
The RAM is an interleaved-access memory, which means that access to the RAM is timeshared
between the CPU Interface Logic and the CAN Bus.
4.1.3 CPU Interface
The IA82527 is capable of interfacing to many commonly used microcontrollers. There are four
parallel interface options and a serial interface option.
Different interface options, or modes, are selected using interface mode pins, mode1 and
mode0. The parallel interface modes that can be selected are as follows:
• 8-bit Intel^® multiplexed address and data buses
• 16-bit Intel^® multiplexed address and data buses
• 8-bit non- Intel^® multiplexed address and data buses
• 8-bit non-multiplexed address and data buses
The serial interface mode is fully compatible with the Motorola^® SPI protocol and will interface to
most commonly used serial interfaces. The serial interface is implemented in slave mode only,
and responds to the master using the specially designed serial interface protocol. The serial
interface mode interconnection scheme is shown in Figure 4.
Copyright  2007
©
Figure 4. mosi/miso Connection
EN21070504-00
Page 22 of 45
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