IA82527 Datasheet, PDF (15/45 Pages) InnovASIC, Inc – Serial Communications Controller CAN Protocol

IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
Table 3. IA82527 Pin/Signal Descriptions, continued
continued . . .
Signal
rd_n
ready
reset_n
r-w_n
rx0
rx1
sclk
Name
Pin
PLCC
rd_n/e
6
ready/miso
28
—
29
wr_n/wrl_n/r-w_n
7
—
22
—
21
a6/ad6/sclk
40
Description
QFP
read. Input. Active Low. Mode 0 and Mode 1.
44 When rd_n is asserted (low), it causes the IA82527 to drive the data
from the location being read onto the data bus.
ready. Output (open drain). Active High. Mode 0 and Mode 1.
22
When ready is asserted (high), it signals the completion of a bus
cycle. The ready output is provided to force system CPU wait states
as required.
reset. Input. Active Low.
When the reset_n signal is asserted (low), the IA82527 is initialized.
There are two reset situations:
Cold Reset. This is a power-on reset: As VCC is driven to a valid
23 ^{level (power on), the reset_n signal must be driven low for a}
minimum of 1 ms measured from a valid VCC level. No falling edge
on the reset_n pin is required during a cold reset.
Warm Reset. For this reset, VCC remains at a valid level (i.e., power
is already on and remains on) while reset_n is driven low for a
minimum of 1 ms.
read-write. Input. Active High (read)-Active Low (write). Mode 3.
1 When r-w_n is high, it signals a read cycle. When r-w_n is low, it
signals a write cycle.
Receive (rx), lines 0 and 1. Input.
Pins rx0 and rx1 are the inputs to the IA82527 from the Controller
Area Network (CAN) bus lines. These pins connect internally to the
receiver input comparator. Serial data from the CAN bus can be
16 ^{received using both rx0 and rx1 or by using only rx0 as follows:}
• When the CoBy Bit in the Bus Configuration Register (2FH) is
a 0, rx0 and rx1 are connected to the input comparator. (rx0
is connected to the non-inverting input and rx1 is connected
to the inverting input.) A recessive level is read when rx0 >
rx1. A dominant level is read when rx1 > rx0.
• When the CoBy Bit in the Bus Configuration Register (2FH) is
a 1, input comparison is disabled, and rx0, which is still
15
connected to the non-inverting input of the comparator, is the
CAN bus line input. For this configuration, the DcR0 bit of the
Bus Configuration Register must be a 0.
After a cold reset (power on), the default configuration is the use of
both rx0 and rx1 for the CAN bus input.
serial clock. Input. Serial Interface Mode.
34 The sclk pin is the serial clock input to the IA82527 (slave device).
The clock signal is provided by the master device.
continued . . .
Copyright  2007
©
EN21070504-00
Page 15 of 45
www.Innovasic.com
Customer Support:
1-888-824-4184