IA82527 Datasheet, PDF (10/45 Pages) InnovASIC, Inc – Serial Communications Controller CAN Protocol

IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
2.2 Pin/Signal Descriptions
Descriptions of the pin and signal functions for the IA82527 Serial Communications Controller
are provided in Table 3.
Several of the IA82527 pins have different functions depending on the operating mode of the
device. Each of the different signals supported by a pin is listed and defined in Table 3, indexed
alphabetically in the first column of the table. Additionally, the name of the pin associated with
the signal as well as the pin numbers for both the PLCC and QFP packages are provided in the
“Pin” column. If the signal and pin names are the same, no entry is provided in the “Pin-Name”
column.
Table 3. IA82527 Pin/Signal Descriptions
Signal
a0
a1
a2
a3
a4
a5
a6
a7
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ad8
ad9
ad10
ad11
ad12
ad13
ad14
ad15
Name
a0/ad0/icp
a1/ad1/cp
a2/ad2/csas
a3/ad3/ste
a4/ad4/mosi
a5/ad5
a6/ad6/sclk
a7/ad7
a0/ad0/icp
a1/ad1/cp
a2/ad2/csas
a3/ad3/ste
a4/ad4/mosi
a5/ad5
a6/ad6/sclk
a7/ad7
ad8/d0/p1.0
ad9/d1/p1.1
ad10/d2/p1.2
ad11/d3/p1.3
ad12/d4/p1.4
ad13/d5/p1.5
ad14/d6/p1.6
ad15/d7/p1.7
Pin
PLCC
4
3
2
43
42
41
40
39
4
3
2
43
42
41
40
39
38
37
36
35
34
33
32
31
QFP
42
41
40
37
36
35
34
33
42
41
40
37
36
35
34
33
32
31
30
29
28
27
26
25
ale
ale/as
5
43
Description
address bits 7–0. Input. Mode 3.
When the IA82527 is configured to operate in the 8-bit non-
multiplexed non-Intel^® architecture mode (Mode 3), these lines
provide the 8-bit address bus input to the device.
address/data bits 15–0. Input/Output. Mode 1.
When the IA82527 is configured to operate in the 16-bit multiplexed
Intel^® architecture mode (Mode 1), these lines provide the 16-bit
address bus (input) and the 16-bit data bus (input/output) for the
device.
address latch enable. Input. Active High. Mode 0 and Mode 1.
When the IA82527 is configured to operate in either the 8-bit
multiplexed Intel^® architecture mode (Mode 0) or the 16-bit
multiplexed Intel^® architecture mode (Mode 1), this signal latches the
address into the device during the address phase of the bus cycle.
continued . . .
Copyright  2007
©
EN21070504-00
Page 10 of 45
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