IA82527 Datasheet, PDF (27/45 Pages) InnovASIC, Inc – Serial Communications Controller CAN Protocol

IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
Table 8. Mode 0 and Mode 1 General Bus and ready Timing
Symbol
Parameter
1/t_XTAL
1/t_SCLK
1/t_MCLK
t_AVLL
t_LLAX
t_LHLL
t_LLRL
t_CLLL
t_QVWH
t_WHQX
t_WLWH
t_WHLH
t_WHCH
t_RLRH
t_RLDV
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to ale Low
Address Hold after ale Low
ale High Time
ale Low to rd_n Low
cs_n Low to ale Low
Data Setup to wr_n or wrh_n High
Input Data Hold after wr_n or wrh_n High
wr_n or wrh_n Pulse Width
wr_n or wrh_n High to Next ale High
wr_n or wrh_n High to cs_n High
rd_n Pulse Width
This time is long enough to initiate a double read
cycle by loading the High Speed Registers (04H,
05H), but is too short to read from 04H and 05H
(see t_RLDV).
rd_n Low to Data Valid
(Only for Registers 02H, 04H, 05H)
t_RLDV1
rd_n Low Data to Data Valid (for all Registers
except 02H, 04H, 05H)
for Read Cycle without a Previous Write
t_RLDV1
t_RHDZ
t_CLYV
t_WLYZ
rd_n Low Data to Data Valid (for all Registers
except 02H, 04H, 05H)
for Read Cycle with a Previous Write
Data Float after rd_n High
cs_n Low to ready Setup
(Load Capacitance on the ready
Output = 50 pF, V_OL = 1.0 V)
cs_n Low to ready Setup
(Load Capacitance on the ready
Output = 50 pF, V_OL = 0.45 V)
wr_n or wrh_n Low to ready Float for a Write
Cycle if No Previous Write is Pending
Minimum
8 MHz
4 MHz
2 MHz
7.5 ns
10 ns
30 ns
20 ns
10 ns
27 ns
10 ns
30 ns
8 ns
0 ns
Maximum
16 MHz
10 MHz
8 MHz
—
—
—
—
—
—
—
—
—
—
40 ns
—
0 ns
55 ns
—
1.5 t_MCLK + 100 ns
—
3.5 t_MCLK + 100 ns
0 ns
45 ns
—
32 ns
—
40 ns
—
145 ns
continued . . .
Copyright  2007
©
EN21070504-00
Page 27 of 45
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