IA82527 Datasheet, PDF (12/45 Pages) InnovASIC, Inc – Serial Communications Controller CAN Protocol

IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
Table 3. IA82527 Pin/Signal Descriptions, continued
Signal
Name
dsack0_n
—
e
rd_n/e
icp
a0/ad0/icp
int_n/ VCC/2
int_n
int_n/p2.6
Pin
PLCC QFP
9
3
6
44
4
42
24
18
11
5
Description
data and size acknowledge 0. Output. Active Low (open drain with
active pull-up). Mode 3 (asynchronous operation).
When the IA82527 is configured to operate in the 8-bit non-
multiplexed non-Intel^® architecture mode (Mode 3), this signal
functions as follows: when the CPU reads from the IA82527,
dsack0_n active low indicates that the data are valid; when the CPU
writes to the IA82527, dsack0_n active low indicates that the data
have been received.
enable. Input. Active High. Mode 3 (asynchronous).
When the IA82527 is configured to operate in the 8-bit non-
multiplexed non-Intel^® architecture mode (Mode 3), this signal
functions as follows: when the CPU reads from or writes to the
IA82527, e active high indicates that the address is valid.
idle clock polarity. Input. Serial Interface Mode.
When this input is a logic 0, the polarity for the idle state of sclk is
low. When this input is a logic 1, the polarity for the idle state of sclk
is high.
interrupt. Output (open collector). Active Low.
On the IA82527, two pins can provide the interrupt (int_n) output;
however, depending on the setting of the MUX bit in the CPU
Interface Register (02H), only one of the pins will serve as the source
of int_n as follows:
• PLCC Package:
- When the MUX bit of the CPU Interface Register is 0, pin
24 functions as the int_n output and pin 11 functions as
p2.6.
- When the MUX bit of the CPU Interface Register is 1, pin
11 functions as the int_n output and pin 24 functions as
Vcc/2.
• QFP Package:
- When the MUX bit of the CPU Interface Register is 0, pin
18 functions as the int_n output and pin 5 functions as
p2.6.
- When the MUX bit of the CPU Interface Register is 1, pin
5 functions as the int_n output and pin 18 functions as
Vcc/2.
continued . . .
Copyright  2007
©
EN21070504-00
Page 12 of 45
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