IA82527 Datasheet, PDF (11/45 Pages) InnovASIC, Inc – Serial Communications Controller CAN Protocol

IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
Table 3. IA82527 Pin/Signal Descriptions, continued
Signal
Name
Pin
PLCC QFP
as
ale/as
5
43
clkout
—
27
21
cp
a1/ad1/cp
3
41
cs_n
—
8
2
csas
d0
d1
d2
d3
d4
d5
d6
d7
a2/ad2/csas
ad8/d0/p1.0
ad9/d1/p1.1
ad10/d2/p1.2
ad11/d3/p1.3
ad12/d4/p1.4
ad13/d5/p1.5
ad14/d6/p1.6
ad15/d7/p1.7
2
40
38
32
37
31
36
30
35
29
34
28
33
27
32
26
31
25
Description
address strobe. Input. Active High. Mode 2.
When the IA82527 is configured to operate in either the 8-bit
multiplexed non-Intel^® architecture mode (Mode 2), this signal latches
the address into the device during the address phase of the bus
cycle.
NOTE: If the IA82527 is configured to operate in Mode 3 (8-bit non-
multiplexed non-Intel^® architecture), this pin must be tied high.
clock out. Output (push-pull).
This output provides a programmable clock frequency. The
frequency is set via the Clockout Register (1FH) and can range from
the frequency of the xtal (crystal) input to xtal/n, where n can be an
integer value from 2 through 15. This output allows the IA82527 to
clock other devices such as the host CPU.
clock phase. Input. Serial Interface Mode.
When this input is a logic 0, data are sampled on the rising edge of
sclk. When this input is a logic 1, data are sampled on the falling
edge of sclk.
chip select. Input. Active Low (Modes 0–3); Selectable Active Level
(Serial Interface Mode).
When the IA82527 is configured to operate in one of the parallel
interface modes (Modes 0–3) or the Serial Interface Mode, this input,
during its active state, selects the device allowing CPU access.
For Serial Interface Mode operation, the active state is selectable
(i.e., either high or low) via the IA8257 csas pin.
chip select active state. Input. Serial Interface Mode.
When this input is a logic 0, the cs_n input is configured to function
active low. When this input is a logic 1, the cs_n input is configured
to function active high.
data bits 7–0. Input/Output. Mode 3.
When the IA82527 is configured to operate in the 8-bit non-
multiplexed non-Intel^® architecture mode (Mode 3), these lines
provide the 8-bit data bus to the device.
continued . . .
Copyright  2007
©
EN21070504-00
Page 11 of 45
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