IA82527 Datasheet, PDF (32/45 Pages) InnovASIC, Inc – Serial Communications Controller CAN Protocol

IA82527
CAN Serial Communications Controller
As of Production Ver. 00
Table 9. Mode 2 General Bus Timing
04 May 2007
PRELIMINARY
Symbol
Parameter
1/t_XTAL
1/t_SCLK
1/t_MCLK
t_AVSL
t_SLAX
t_ELDZ
t_EHDV
t_QVEL
t_ELQX
t_ELDV
t_EHEL
t_SHSL
t_RSEH
t_SLEH
t_CLSL
t_ELCH
t_COPD
t_CHCL
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to as Low
Address Hold after as Low
Data Float after e Low
e High to Data Valid for Registers 02H,
04H, 05H
e High to Data Valid (all Registers except
for 02H, 04H, 05H) for Read Cycle without a
Previous Write
e High to Data Valid (all Registers except
for 02H, 04H, 05H) for Read Cycle with a
Previous Write
Data Setup to e Low
Input Data Hold after e Low
e Low to Output Data Valid on Port 1/2
e High Time
as High Time
Setup Time of r-w_n to e High
as Low to e High
cs_n Low to as Low
e Low to cs_n High
clkout Period
(CD_V is the value loaded in the CLKOUT
Register representing the clkout divisor.)
clkout High Period
(CD_V is the value loaded in the CLKOUT
Register representing the clkout divisor.)
Minimum
8 MHz
4 MHz
2 MHz
7.5 ns
10 ns
0 ns
0 ns
Maximum
16 MHz
10 MHz
8 MHz
45 ns
45 ns
—
1.5 t_mclk + 100 ns
—
3.5 t_mclk + 100 ns
30 ns
20 ns
t_mclk
45 ns
30 ns
30 ns
20 ns
20 ns
0 ns
—
—
2 t_mclk + 500 ns
—
—
—
—
—
(CDV + 1) ^• tosc
(CDV + 1) ^• ½ tosc – 10
(CDV + 1) ^• ½ tosc – 15
Copyright  2007
©
EN21070504-00
Page 32 of 45
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