IA82527 Datasheet, PDF (34/45 Pages) InnovASIC, Inc – Serial Communications Controller CAN Protocol

IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
Table 10. Mode 3 Asynchronous Operation Timing
Symbol
Parameter
1/t_XTAL
1/t_SCLK
1/t_MCLK
t_AVCL
t_CLDV
t_KLDV
t_CHDV
t_CHDH
t_CHDZ
t_CHKH1
t_CHKH2
t_CHKZ
t_CHCL
t_CHAI
t_CLCH
t_DVCH
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address or r-w_n Valid to cs_n Low
Setup
cs_n Low to Data Valid
(for High-Speed Registers 02H, 04H, and
05H)
cs_n Low to Data Valid
(for Low-Speed Registers)
Read Cycle without Previous Write
cs_n Low to Data Valid
(for Low-Speed Registers)
Read Cycle with Previous Write
dsack0_n Low to Output Data Valid
(for High-Speed Read Registers)
dsack0_n Low to Output Data Valid
(for Low-Speed Read Registers)
Input Data Hold after cs_n High
Output Data Hold after cs_n High
cs_n High to Output Data Float
cs_n High to dsack0_n = 2.4V
(An on-chip pull-up will drive dsack0_n to
approximately 2.4V; an external pull-up is
required to drive this signal to a higher
voltage.)
cs_n High to dsack0_n = 2.8V
cs_n High to dsack0_n Float
cs_n Width between Successive Cycles
cs_n High to Address Invalid
cs_n Width Low
CPU Write Data Valid to cs_n High
Minimum
8 MHz
4 MHz
2 MHz
3 ns
0 ns
Maximum
16 MHz
10 MHz
8 MHz
—
55 ns
0 ns
1.5 t_mclk + 100 ns
0 ns
—
< 0 ns
15 ns
0 ns
—
3.5 t_mclk + 100 ns
23 ns
—
—
—
35 ns
0 ns
55 ns
—
0 ns
25 ns
7 ns
65 ns
20 ns
150 ns
100 ns
—
—
—
—
continued . . .
Copyright  2007
©
EN21070504-00
Page 34 of 45
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