XC2723X Datasheet, PDF (98/109 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2723X
XC2000 Family / Econo Line
Electrical Parameters
4.7.6 Debug Interface Timing
The debugger can communicate with the XC2723X via 1-pin SPD interface, via the 2-pin
DAP interface or via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 36 is valid under the following conditions: C_L= 20 pF; voltage_range= upper
Table 36 DAP Interface Timing for Upper Voltage Range
Parameter
DAP0 clock period
DAP0 high time
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Symbol
Min.
t₁₁ SR
t₁₂ SR
t₁₃ SR
t₁₄ SR
t₁₅ SR
t₁₆ SR
100¹⁾
8
8
−
−
6
Values
Typ. Max.
−
−
−
−
−
−
−
4
−
4
−
−
Unit Note /
Test Condition
ns
ns
ns
ns
ns
ns pad_type= stan
dard
DAP1 hold after DAP0 t₁₇ SR 6
−
−
ns pad_type= stan
rising edge
dard
DAP1 valid per DAP0
t₁₉ CC 92
95
−
clock period²⁾
ns pad_type= stan
dard
1) The debug interface cannot operate faster than the overall system, therefore t₁₁ ≥ t_SYS.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
Data Sheet
94
V1.2, 2012-07