English
Language : 

XC2723X Datasheet, PDF (76/109 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
◁
XC2723X
XC2000 Family / Econo Line
Electrical Parameters
Table 23 A/D Converter Computation Table
GLOBCTR.5-0 A/D Converter
INPCRx.7-0
Sample Time1)
(DIVA)
Analog Clock fADCI
(STC)
tS
000000B
fSYS
00H
tADCI × 2
000001B
fSYS / 2
01H
tADCI × 3
000010B
fSYS / 3
02H
tADCI × 4
:
fSYS / (DIVA+1)
:
tADCI × (STC+2)
111110B
fSYS / 63
FEH
tADCI × 256
111111B
fSYS / 64
FFH
tADCI × 257
1) The selected sample time is doubled if broken wire detection is active (due to the presampling phase).
Converter Timing Example A:
Assumptions: fSYS
Analog clock
fADCI
Sample time
tS
Conversion 12-bit:
tC12
Conversion 10-bit:
tC10
Conversion 8-bit:
tC8
= 80 MHz (i.e. tSYS = 12.5 ns), DIVA = 03H, STC = 00H
= fSYS / 4 = 20 MHz, i.e. tADCI = 50 ns
= tADCI × 2 = 100 ns
= 16 × tADCI + 2 × tSYS = 16 × 50 ns + 2 × 12.5 ns = 0.825 μs
= 12 × tADCI + 2 × tSYS = 12 × 50 ns + 2 × 12.5 ns = 0.625 μs
= 10 × tADCI + 2 × tSYS = 10 × 50 ns + 2 × 12.5 ns = 0.525 μs
Converter Timing Example B:
Assumptions: fSYS
Analog clock
fADCI
Sample time
tS
Conversion 12-bit:
tC12
Conversion 10-bit:
tC10
= 66 MHz (i.e. tSYS = 15.2 ns), DIVA = 03H, STC = 00H
= fSYS / 4 = 16.5 MHz, i.e. tADCI = 60.6 ns
= tADCI × 2 = 121.2 ns
= 16 × tADCI + 2 × tSYS = 16 × 60.6 ns + 2 × 15.2 ns = 1.0 μs
= 12 × tADCI + 2 × tSYS = 12 × 60.6 ns + 2 × 15.2 ns = 0.758 μs
Data Sheet
72
V1.2, 2012-07
 ▷