XC2723X Datasheet, PDF (85/109 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2723X
XC2000 Family / Econo Line
Electrical Parameters
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11_B), the system clock is
derived directly from the input clock signal CLKIN1:
f_SYS = f_IN.
The frequency of f_SYS is the same as the frequency of f_IN. In this case the high and low
times of f_SYS are determined by the duty cycle of the input clock f_IN.
Selecting Bypass Operation from the XTAL1¹⁾ input and using a divider factor of 1 results
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10_B, PLLCON0.VCOBY =
1_B), the system clock is derived either from the crystal oscillator (input clock signal
XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1):
f_SYS = f_OSC / K1.
If a divider factor of 1 is selected, the frequency of f_SYS equals the frequency of f_OSC. In
this case the high and low times of f_SYS are determined by the duty cycle of the input
clock f_OSC (external or internal).
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
f_SYS = f_OSC / 1024.
4.7.2.1 Phase Locked Loop (PLL)
When PLL operation is selected (SYSCON0.CLKSEL = 10_B, PLLCON0.VCOBY = 0_B),
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (f_SYS = f_IN × F).
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P × K2)).
The input clock can be derived either from an external source at XTAL1 or from the on-
chip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of f_SYS so that it is
locked to f_IN. The slight variation causes a jitter of f_SYS which in turn affects the duration
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage V_DDIM.
Data Sheet
81
V1.2, 2012-07