XC2723X Datasheet, PDF (28/109 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2723X
XC2000 Family / Econo Line
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC2723X is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8
XC2723X Memory Map ¹⁾
Address Area
Start Loc. End Loc. Area Size²⁾ Notes
IMB register space
Reserved
FF’FF00_H FF’FFFF_H 256 bytes
F0’0000_H FF’FEFF_H < 1 Mbyte
Minus IMB
registers.
Reserved for EPSRAM
Emulated PSRAM
Reserved for PSRAM
PSRAM
Reserved for Flash
Flash 1
Reserved for Flash
Flash 0
External memory area
External IO area⁴⁾
Reserved
USIC0-1 alternate regs.
E8’1000_H
E8’0000_H
E0’1000_H
E0’0000_H
C4’8000_H
C4’0000_H
C2’1000_H
C0’0000_H
40’0000_H
21’0000_H
20’B800_H
20’B000_H
EF’FFFF_H
E8’0FFF_H
E7’FFFF_H
E0’0FFF_H
DF’FFFF_H
C4’7FFF_H
C3’FFFF_H
C2’0FFF_H
BF’FFFF_H
3F’FFFF_H
20’FFFF_H
20’B7FF_H
508 Kbytes Mirrors EPSRAM
up to 4 Kbytes With Flash timing.
508 Kbytes Mirrors PSRAM
up to 4 Kbytes Program SRAM.
1760 Kbytes
32 Kbytes
124 Kbytes
132 Kbytes³⁾
8 Mbytes
1984 Kbytes
18 Kbytes
2 Kbytes
Accessed via
LXBus Controller
MultiCAN alternate regs. 20’8000_H 20’AFFF_H 12 Kbytes
Accessed via
LXBus Controller
Reserved
USIC0-1 registers
20’5000_H 20’7FFF_H 12 Kbytes
20’4000_H 20’4FFF_H 4 Kbytes
Accessed via
LXBus Controller
MultiCAN registers
20’0000_H 20’3FFF_H 16 Kbytes
Accessed via
LXBus Controller
External memory area
SFR area
Dual-port RAM
(DPRAM)
01’0000_H
00’FE00_H
00’F600_H
1F’FFFF_H
00’FFFF_H
00’FDFF_H
1984 Kbytes
0.5 Kbytes
2 Kbytes
Reserved for DPRAM 00’F200_H 00’F5FF_H 1 Kbytes
Data Sheet
24
V1.2, 2012-07