XC2723X Datasheet, PDF (29/109 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2723X
XC2000 Family / Econo Line
Functional Description
Table 8
XC2723X Memory Map (cont’d)¹⁾ (cont’d)
Address Area
Start Loc. End Loc. Area Size²⁾ Notes
ESFR area
00’F000_H 00’F1FF_H 0.5 Kbytes
XSFR area
00’E000_H 00’EFFF_H 4 Kbytes
Data SRAM (DSRAM) 00’C800_H 00’DFFF_H 6 Kbytes
Reserved for DSRAM 00’8000_H 00’C7FF_H 18 Kbytes
External memory area 00’0000_H 00’7FFF_H 32 Kbytes
1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
external bus accesses.
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000_H to C0’FFFF_H).
4) Several pipeline optimizations are not active within the external IO area.
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
4 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is optimized for code fetches. A section of the
PSRAM with programmable size can be write-protected.
Data Sheet
25
V1.2, 2012-07