XC2723X Datasheet, PDF (52/109 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2723X
XC2000 Family / Econo Line
Functional Description
When clocked by f_SYS = 80 MHz, time intervals between 12.5 ns and 13.4 s can be
monitored.
When clocked by f_WU = 500 kHz, time intervals between 2.0 µs and 2147.5 s can be
monitored.
The default Watchdog Timer interval after power-up is 0.13 s (@ f_WU = 500 kHz).
3.16
Clock Generation
The Clock Generation Unit can generate the system clock signal f_SYS for the XC2723X
from a number of external or internal clock sources:
• External clock signals with pad voltage or core voltage levels
• External crystal or resonator using the on-chip oscillator
• On-chip clock source for operation without crystal/resonator
• Wake-up clock (ultra-low-power) to further reduce power consumption
The programmable on-chip PLL with multiple prescalers generates a clock signal for
maximum system performance from standard crystals, a clock input signal, or from the
on-chip clock source. See also Section 4.7.2.
The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency
falls below a certain limit or stops completely. In this case, the system can be supplied
with an emergency clock to enable operation even after an external clock failure.
All available clock signals can be output on the EXTCLK pin.
Data Sheet
48
V1.2, 2012-07