HYB25D512400AT Datasheet, PDF (9/76 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[16/40/80]0AT–[6/7/7F]
Pin Configuration
Table 3 Input/Output Functional Description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of CK.
Output (read) data is referenced to the crossings of CK and CK (both directions of
crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE Low provides Precharge
Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit, and for self
refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained
high throughout read and write accesses. Input buffers, excluding CK, CK and CKE
are disabled during power-down. Input buffers, excluding CKE, are disabled during
self refresh.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides
for external bank selection on systems with multiple banks. CS is considered part of
the command code. The standard pinout includes one CS pin.
RAS, CAS, WE Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. LDM and UDM are the input mask signals for ×16
components and control the lower or upper bytes. For ×8 components the data mask
function is disabled, when RDQS / RQDS are enabled by EMRS(1) command.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. BA0 and BA1 also determines if the mode
register or extended mode register is to be accessed during a MRS or EMRS cycle.
A0 - A12
Input
Address Inputs: Provide the row address for Active commands, and the column
address and Auto Precharge bit for Read/Write commands, to select one location out
of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during a Mode Register Set
command.
DQ
Input/ Data Input/Output: Data bus.
Output
DQS, (DQS) Input/
LDQS, (LDQS), Output
UDQS,(UDQS)
Data Strobe: output with read data, input with write data. Edge aligned with read
data, centered with write data. For the ×16, LDQS corresponds to the data on
LDQ[0:7]; UDQS corresponds to the data on UDQ[0:7]. The data strobes DQS,
LDQS, UDQS may be used in single ended mode or paired with the optional
complementary signals DQS, LDQS, UDQS to provide differential pair signaling to
the system during both reads and writes. An EMRS(1) control bit enables or disables
the complementary data strobe signals.
N.C.
–
No Connect: No internal electrical connection is present.
V_DDQ
V_SSQ
V_DD
V_SS
V_REF
Supply
Supply
Supply
Supply
Supply
DQ Power Supply: 2.5 V ± 0.2 V.
DQ Ground
Power Supply: 2.5 V ± 0.2 V.
Ground
SSTL_2 Reference Voltage: (V_DDQ /2)
Data Sheet
9
Rev. 1.0, 2004-03