HYB25D512400AT Datasheet, PDF (10/76 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[16/40/80]0AT–[6/7/7F]
Pin Configuration
Drivers
Receivers
Read Latch
Bank0
Row-Address Latch
& Decoder
Bank Control Logic
Row-Address MUX
Refresh Counter
Address Register
Figure 2 Block Diagram 128 Mbit × 4
Note:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and
DQS signals.
Data Sheet
10
Rev. 1.0, 2004-03