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| HYB25D512400AT Datasheet, PDF (62/76 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM | |||
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HYB25D512[16/40/80]0ATâ[6/7/7F]
Electrical Characteristics
4.5
IDD1: Operating Current: One Bank Operation
1. Only one bank is accessed with tRCMIN. Burst Mode, Address and Control inputs on NOP edge are changing
once per clock cycle. IOUT = 0 mA.
2. Timing patterns
a) DDR200 (100 MHz, CL = 2): tCK = 10 ns, CL = 2, BL = 4, tRCD = 2 Ã tCK, tRAS = 5 Ã tCK
Setup: A0 N R0 N N P0 N
Read: A0 N R0 N N P0 N - repeat the same timing with random address changing
50% of data changing at every burst
b) DDR266A (133 MHz, CL = 2): tCK = 7.5 ns, CL = 2, BL = 4, tRCD = 3 Ã tCK, tRC = 9 Ã tCK, tRAS = 5 Ã tCK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N NN - repeat the same timing with random address changing
50% of data changing at every burst
c) DDR333 (166 MHz, CL = 2.5): tCK = 6 ns, CL = 2.5, BL = 4, tRCD = 3 Ã tCK, tRC = 9 Ã tCK, tRAS = 5 Ã tCK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N N N - repeat the same timing with random address changing
50% of data changing at every burst
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
IDD7: Operating Current: Four Bank Operation
1. Four banks are being interleaved with tRCMIN. Burst Mode, Address and Control inputs on NOP edge are not
changing. IOUT = 0 mA.
2. Timing patterns
a) DDR200 (100 MHz, CL = 2): tCK = 10 ns, CL = 2, BL = 4, tRRD = 2 Ã tCK, tRCD = 3 Ã tCK, Read with
autoprecharge
Setup: A0 N A1 R0 A2 R1 A3 R2
Read: A0 R3 A1 R0 A2 R1 A3 R2 - repeat the same timing with random address changing
50% of data changing at every burst
b) DDR266A (133 MHz, CL = 2): tCK = 7.5 ns, CL = 2, BL = 4, tRRD = 2 Ã tCK, tRCD = 3 Ã tCK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
c) DDR333 (166 MHz, CL = 2.5): tCK = 6 ns, CL = 2.5, BL = 4, tRRD = 2 Ã tCK, tRCD = 3 Ã tCK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
Data Sheet
62
Rev. 1.0, 2004-03
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