HYB25D512400AT Datasheet, PDF (35/76 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[16/40/80]0AT–[6/7/7F]
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
Maximum DQSS
T1
T2
T3
T4
T5
Write
Write
BAa, COL b
BAa, COL x
t_DQSS (max)
Write
BAa, COL n
Write
BAa, COL a
Write
BAa, COL g
DI a-b DI a-b’
DI a-x
DI a-x’ DI a-n
DI a-n’
DI a-a
DI a-a’
CK
CK
Command
Address
DQS
DQ
DM
Minimum DQSS
T1
T2
T3
T4
T5
Write
Write
BAa, COL b
BAa, COL x
t_DQSS (min)
Write
BAa, COL n
Write
BAa, COL a
Write
BAa, COL g
DI a-b DI a-b’
DI a-x
DI a-x’
DI a-n
DI a-n’
DI a-a
DI a-a’
DI a-g
DI a-b, etc. = data in for bank a, column b, etc.
b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).
Each Write command may be to any bank.
Don’t Care
Figure 20 Random Write Cycles (Burst Length = 2, 4 or 8)
Data Sheet
35
Rev. 1.0, 2004-03