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HYB25D512400AT Datasheet, PDF (26/76 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM
CK
CK
Command
Address
DQS
DQ
HYB25D512[16/40/80]0AT–[6/7/7F]
Functional Description
CAS Latency = 2
Read
BAa, COL n
Read
BAa, COL x
CL=2
Read
BAa, COL b
Read
BAa, COL g
NOP
NOP
DOa-n DOa-n’ DOa-x DOa-x’ DOa-b DOa-b’ DOa-g
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2.5
Read
BAa, COL n
Read
Read
BAa, COL x
BAa, COL b
CL=2.5
Read
BAa, COL g
NOP
NOP
DOa-n DOa-n’ DOa-x DOa-x’ DOa-b DOa-b’
DO a-n, etc. = data out from bank a, column n etc.
n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).
Reads are to active rows in any banks.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Don’t Care
Figure 12 Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
Data from any Read burst may be truncated with a Burst Terminate command, as shown on Figure 13. The Burst
Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles
after the Read command, where x equals the number of desired data element pairs.
Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If
truncation is necessary, the Burst Terminate command must be used, as shown on Figure 14. The example is
shown for tDQSS(min). The tDQSS(max) case, not shown here, has a longer bus idle time. tDQSS(min) and tDQSS(max) are
defined in Chapter 3.5.3.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto
Precharge was not activated). The Precharge command should be issued x cycles after the Read command,
where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This
is shown on Figure 15 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent
command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden
during the access of the last data elements.
Data Sheet
26
Rev. 1.0, 2004-03