HYB25D512400AT Datasheet, PDF (33/76 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[16/40/80]0AT–[6/7/7F]
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
CK
CK
Command
Address
DQS
DQ
DM
T1
T2
T3
Write
NOP
BAa, COL b
t_DQSS (max)
Write
BAa, COL n
DI a-b
T4
NOP
Maximum DQSS
T5
T6
NOP
NOP
DI a-n
T1
T2
T3
T4
Write
BA, COL b
NOP
Write
t_DQSS (min)
BA, COL n
NOP
DI a-b
DI a-n
Minimum DQSS
T5
T6
NOP
NOP
DI a-b = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
3 subsequent elements of data in are applied in the programmed order following DI a-n.
A non-interrupted burst is shown.
Each Write command may be to any bank.
Figure 18 Write to Write (Burst Length = 4)
Don’t Care
Data Sheet
33
Rev. 1.0, 2004-03