HYB25D512400AT Datasheet, PDF (12/76 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[16/40/80]0AT–[6/7/7F]
Pin Configuration
Drivers
Receivers
Read Latch
Bank0
Row-Address Latch
& Decoder
Bank Control Logic
Row-Address MUX
Refresh Counter
Address Register
Figure 4 Block Diagram 32 Mbit × 16
Note:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. UDM and LDM are unidirectional signals (input only), but is internally loaded to match the load of the
bidirectional DQ, UDQS and LDQS signals.
Data Sheet
12
Rev. 1.0, 2004-03