TC1115 Datasheet, PDF (83/103 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller Advance Information

TC1115
Advance Information
Electrical Parameters
4.3.2 PLL Parameters
When PLL operation is configured (PLL_CLC.LOCK = 1), the on-chip phase locked loop
is enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (f_MC = f_OSC × F) which results from the input divider, the multiplication factor (N
Factor), and the output divider (F = NDIV+1 / (PDIV+1 × KDIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock, the frequency of f_MC is constantly adjusted so
it is locked to f_OSC. The slight variation causes a jitter of f_MC which also affects the
duration of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because f_CPU is derived from
f_MC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency in order to correspond to the applied input
frequency (crystal or oscillator), the relative deviation for periods of more than one TCP
is lower than for one single TCP (see formula and Figure 4-2).
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baud rates, etc.) the deviation caused by the PLL
jitter is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = KDIV+1) to generate the master clock signal f_MC. Therefore, the
number of VCO cycles can be represented as K × N, where N is the number of
consecutive f_MC cycles (TCM).
For a period of N × TCM, the accumulated PLL jitter is defined by the corresponding
deviation D_N:
D_N [ns] = ±(1.5 + 6.32 × N / f_MC); f_MC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D₃ = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K × N < 95. For longer periods, the K×N=95 value can be
used. This steady value can be approximated by: D_Nmax [ns] = ±(1.5 + 600 / (K × f_MC)).
Data Sheet
77
V1.0, 2005-02